Architectural and compiler techniques for energy reduction inhigh-performance microprocessors

摘要

In this paper, we focus on low-power design techniques fornhigh-performance processors at the architectural and compiler levels. Wenfocus mainly on developing methods for reducing the energy dissipated innthe on-chip caches. Energy dissipated in caches represents a substantialnportion in the energy budget of today's processors. Extrapolatingncurrent trends, this portion is likely to increase in the near future,nsince the devices devoted to the caches occupy an increasingly largernpercentage of the total area of the chip. We propose a method that usesnan additional minicache located between the I-Cache and the centralnprocessing unit (CPU) core and buffers instructions that are nestednwithin loops and are continuously otherwise fetched from the I-Cache.nThis mechanism is combined with code modifications, through thencompiler, that greatly simplify the required hardware, eliminatenunnecessary instruction fetching, and consequently reduce signalnswitching activity and the dissipated energy. We show that thenadditional cache, dubbed L-Cache, is much smaller and simpler than thenI-Cache when the compiler assumes the role of allocating instructions tonit. Through simulation, we show that for the SPECfp95 benchmarks, thenI-Cache remains disabled most of the time, and the “cheaper”nextra cache is used instead. We also propose different techniques thatnare better adapted to nonnumeric nonloop-intensive code