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Hardware/software codesign of finite field datapath for low-energyReed-Solomon codecs

机译:低能耗Reed-Solomon编解码器的有限域数据路径的硬件/软件代码

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Reed-Solomon (RS) coders are used for error-control coding in manynapplications such as digital audio, digital TV, software radio, CDnplayers, and wireless and satellite communications. Traditionally, RSncoders have been implemented using dedicated hardware. This papernconsiders software-based implementation of RS codecs. Anhardware-software codesign approach is used to design the finite fieldndatapath in a domain-specific digital signal processor (DSP) withnlow-energy RS codecs application in mind. These datapaths are designednto accommodate programmability with respect to the primitive polynomialnas well as the field degree m. A novel heterogeneous digit-serialnapproach is proposed, where the heterogeneity corresponds to the use ofndifferent digit sizes in the multiply-accumulate (MAC) and degreenreduction (DEGRED) subarrays. The salient feature of this digit-serialnapproach is that only the digit cells are implemented in hardware andnthe finite field multiplications are performed digit-serially innsoftware by dynamically scheduling the internal digit-level operations.nEfficient scheduling strategies for digit-serial finite fieldnmultiplications are presented and applied to the design of low-energynhigh-performance RS codecs in software. Significant energy andnenergy-latency reductions can be achieved using the digit-serialndatapaths, as compared with the traditional approach where a combinednMAC-DEGRED (parallel multiplier) unit is used. It is concluded that forntwo-error-correcting RS(n, k) codes over finite field GF(28),ndatapath containing a parallel MAC unit (of digit size eight) and anDEGRED unit with digit size two (or four) leads to RS codecs with thenleast energy consumption and energy-latency products; with thesendatapath architectures and appropriate digit-serial schedulingnstrategies, more than 60% energy reduction and more than one-thirdnenergy-latency reduction can be achieved compared with the parallelnmultiplication datapath-based approach
机译:Reed-Solomon(RS)编码器用于许多应用程序中的错误控制编码,例如数字音频,数字电视,软件无线电,CDnplayer和无线和卫星通信。传统上,RSncoders是使用专用硬件实现的。本文考虑了基于软件的RS编解码器实现。在考虑到低能耗RS编解码器应用的情况下,使用硬件-软件代码签名方法来设计域专用数字信号处理器(DSP)中的有限域数据路径。设计这些数据路径以适应相对于原始多项式以及场度m的可编程性。提出了一种新颖的异构数字串行方法,其中异质性对应于乘法累加(MAC)和度数减少(DEGRED)子阵列中不同数字大小的使用。这种数字串行方法的显着特征是,只有数字单元在硬件中实现,并且有限域乘法是通过动态调度内部数字级运算在软件中以数字串行方式执行的。n提出了用于数字串行有限域n乘法的高效调度策略,应用于软件中的低能耗高性能RS编解码器的设计。与使用组合的MAC-DEGRED(并行乘法器)单元的传统方法相比,使用数字串行数据路径可以显着降低能量和能量延迟。得出结论,在有限域GF(28)上进行forntwo纠错的RS(n,k)码,包含并行MAC单元(位数为八位)和DEGRED单元为位数为二(或四位)的ndatapath导致RS具有最低能耗和能源延迟产品的编解码器;与基于并行乘法数据路径的方法相比,借助sendatapath架构和适当的数字串行调度策略,可以实现60%以上的能耗降低和三分之一以上的能耗延迟

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