Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

摘要

A closed-form expression for the propagation delay of a CMOS gatendriving a distributed RLC line is introduced that is within 5% ofndynamic circuit simulations for a wide range of RLC loads. It is shownnthat the error in the propagation delay if inductance is neglected andnthe interconnect is treated as a distributed RC line can be over 35% forncurrent on-chip interconnect. It is also shown that the traditionalnquadratic dependence of the propagation delay on the length of theninterconnect for RC lines approaches a linear dependence as inductanceneffects increase. On-chip inductance is therefore expected to have anprofound effect on traditional high-performance integrated circuit (IC)ndesign methodologies. The closed-form delay model is applied to thenproblem of repeater insertion in RLC interconnect. Closed-form solutionsnare presented for inserting repeaters into RLC lines that are highlynaccurate with respect to numerical solutions. RC models can createnerrors of up to 30% in the total propagation delay of a repeater systemnas compared to the optimal delay if inductance is considered. The errornbetween the RC and RLC models increases as the gate parasitic impedancesndecrease with technology scaling. Thus, the importance of inductance innhigh-performance very large scale integration (VLSI) designnmethodologies will increase as technologies scale