A reconfigurable multifunction computing cache architecture

摘要

A considerable portion of a microprocessor chip is dedicated toncache memory. However, not all applications need all the cache storagenall the time, especially the computing bandwidth-limited applications.nIn addition, some applications have large embedded computations with anregular structure. Such applications may be able to use additionalncomputing resources. If the unused portion of the cache could serventhese computation needs, the on-chip resources would be utilized morenefficiently. This presents an opportunity to explore the reconfigurationnof a part of the cache memory for computing. Thus, we propose adaptivenbalanced computing (ABC)-dynamic resource configuration on demand fromnapplication-between memory and computing resources. In this paper, wenpresent a cache architecture to convert a cache into a computing unitnfor either of the following two structured computations: finite impulsenresponse and discrete/inverse discrete cosine transform. In order tonconvert a cache memory to a function unit, we include additional logicnto embed multibit output lookup tables into the cache structure. Thenexperimental results show that the reconfigurable module improves thenexecution time of applications with a large number of data elements by anfactor as high as 50 and 60