Unified VLSI systolic array design for LZ data compression

摘要

Hardware implementation of data compression algorithms isnreceiving increasing attention due to exponentially expanding networkntraffic and digital data storage usage. In this paper, we proposenseveral serial one-dimensional and parallel two-dimensionalnsystolic-arrays for Lempel-Ziv data compression. A VLSI chipnimplementing our optimal linear array is fabricated and tested. Thenproposed array architecture is scalable. Also, multiple chips (linearnarrays) can be connected in parallel to implement the parallel arraynstructure and provide a proportional speedup