VLSI design for high-speed LZ-based data compression

摘要

A simple real-time parallel architecture for a CMOS VLSInimplementation of a Ziv-Lempel data compression system is presented.nThis encoding system employs a linear systolic array to findnconcurrently the matches between each input data character and itsncorresponding dictionary, and can easily achieve an ideal compressionnratio by cascading the chips of the encoding cell. A new encodingnarchitecture is proposed to improve the encoding speed and reducenhardware complexity for the encoding cells. In addition, the number ofnmemory accesses is reduced to save power consumption for high-speednapplications. The encoder codes one character (more than eight bits) pernencoding cycle. The clock rate by Verilog simulator can be constrainednbelow 15 ns using the Compass standard cell library for the 0.6 ΜmnCMOS process