Duet: an accurate leakage estimation and optimization tool fordual-Vt circuits

摘要

Presents a new approach for the estimation and optimization ofnstandby power dissipation in large MOS digital circuits. We introduce annew approach for accurate and efficient calculation of the averagenstandby or leakage current in large digital circuits by introducing thenconcepts of "dominant leakage states" and the use of statenprobabilities. Combined with graph reduction techniques and simplifiednnonlinear simulation, the method achieves speedups of three to fournorders of magnitude over exhaustive SPICE simulations while maintainingnvery good accuracy. The leakage current calculation is then utilized inna new leakage and performance optimization algorithm for circuits usingndual Vt processes. The approach is the first to consider thenassignment of both the Vt and the width of a transistor,nsimultaneously. The optimization approach uses incremental calculationnof leakage and performance sensitivities and can take into account anpartially defined circuit state constraint for the standby mode of thendevice