Memory power models for multilevel power estimation andoptimization

摘要

Storage cost is a major factor in the total power consumption ofndigital signal processing circuits. Power models for on-chip memoriesnare consequently an important ingredient in power aware design flows fornestimation and optimization. Unfortunately, exact memory-modelingntechniques are not widely applied in practice. This is mainly due to thenvendors' need for intellectual property protection (IPP), the ill fitninto vendors' design cycles and the significant overhead in time andnmanpower involved. To bridge the gap, between vendors and designers, wensuggest an automatic black box modeling approach. It is based onnnonlinear regression that combines all desired properties: accuracy,nflexibility, speed, low overhead, a good fit into the vendors' designncycle, IP protection, plus a mathematical form that is well suited fornoptimization