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Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

机译:低功耗数据路径综合的新型低开销操作数隔离技术

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Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)
机译:冗余切换导致的数据路径模块功耗是高性能应用的重要设计关注点。减少此冗余切换的操作数隔离方案在延迟,功率和面积方面会产生相当大的开销。本文介绍了基于电源门控的新颖操作数隔离技术,该技术可减少与隔离电路相关的开销。所提出的方案还针对泄漏最小化和在数据路径的内部逻辑处的附加操作数隔离,以进一步降低功耗。我们将提出的技术与功率/延迟模型集成在一起,以开发用于低功率数据路径综合的综合流程。仿真结果表明,与原始电路相比,拟议的操作数隔离技术可将功耗至少降低40%,同时具有最小的面积开销(5%)和延迟损失(0.15%)

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