Low Power Synthesis in Digital Design by Automatic Insertion of Clock Gating and Operand Isolation Cells

摘要

This work presents a design and verification of low power and high performance router by using dynamic power reduction technique i.e. Clock gating and Operand isolation. The power consumption of the presented router is significantly lower than that of a router with unnecessary switching activities. The clock gating and operand isolation techniques allows a variety of features such as easily configurable, automatically implemented which allows maximal reduction in power requirements with minimal designer involvement and software involvement. Clock gating and operand isolation techniques can be introduced into a design manually or tools exist to perform automatically. In this paper, source code was written in Verilog (Hardware Descriptive language), simulation and low power synthesis is done in cadence by using 45nm technology. In this paper a comparison is done on synthesis power report without and with low power techniques, shown that a 68% reduction in total power