Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over Using Multiple Parity Prediction Schemes

摘要

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over ${rm GF}(2^{m})$ using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.