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Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol

机译:通过零知识协议对FPGA设计中IP标记进行安全的公开验证

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In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmable gate-array (FPGA) designs, marks become prone to tampering, and even being overridden by an attacker's signature after public verification. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, we propose a zero-knowledge protocol Verify_ZKP. It is an interactive two-person game between the prover and the verifier. This protocol is fast, incurs no additional design overhead, and needs no centralized signature database. We establish that Verify_ZKP satisfies zero-knowledge property, and introduce statistical metrics to measure its robustness. We have simulated our protocol for IWLS'05 FPGA benchmarks. Experimental results on robustness and overhead are very encouraging.
机译:在纳米技术体系中,设计组件要求其重复使用以应对复杂的设计挑战,因此包含知识产权(IP)。未经授权的重用会引发重大的安全问题。 IP标记被嵌入到设计中以建立合法IP所有者/买方的真实性。但是,对IP标记进行可信赖的公共验证的方法并不安全。对于现场可编程门阵列(FPGA)设计,在公开验证后,标记容易被篡改,甚至被攻击者的签名所覆盖。为了基于FPGA设计中隐藏的标记确保可信赖的防泄漏公共验证,我们提出了一种零知识协议Verify_ZKP。它是证明者与验证者之间的交互式两人游戏。该协议速度很快,不会产生额外的设计开销,并且不需要集中式签名数据库。我们确定Verify_ZKP满足零知识属性,并引入统计指标来衡量其健壮性。我们已经为IWLS'05 FPGA基准仿真了协议。关于鲁棒性和开销的实验结果非常令人鼓舞。

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