The implementation of a huge scale SoC(System-onchip)is becoming difficult task not only due to itscomplexity, but also the design of a more amount ofIPs. A consensus interface protocol for IP cores isbecoming significant and even predictable for asuccessful SoC establishment. OCP, with itscandidness, concerted, not-for-profit nature, andinherent large industry member base, is quicklybecoming a feasible and preferable solution over a closeor an in-house standard. In this project; well-definedinterface standard, the Open Core Protocol (OCP), andfocus on the design of the internal bus architecture. Wedevelop an efficient bus architecture to support mostadvanced bus properties defined in OCP, includingburst transactions, lock transactions, pipelinedtransactions, and out-of-order transactions. on-chip buswith transaction level modelling for the consideration ofdesign flexibility and fast simulation speed is presentedin this project.
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