The implementation of a massive scale SoC (Systemon-chip) is becoming increasingly difficult task notonly because of its complexity, but also the design ofa more amount of IP addresses. A consensusinterfaceprotocol for IP-cores are still significanteven and predictable for a successful establishmentSoC. OCP, with his frankness, coordinated, not-forprofitnature, and the inherent large industrymembership, is quickly becoming a viable andpreferable solution over a narrow or an in-housestandard. In this project, well-defined interfacestandard, the Open Core Protocol (OCP), and focuson the design of the internal bus architecture. Wedevelop an efficient bus architecture to the mostadvanced bus features defined in OCP, includingburst transactions, lock transactions, pipelinedtransactions, and support. Out-of-order transactionson-chip bus transaction level modeling to treat thedesign flexibility and fast simulation speed isproposed in this project.
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