Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate

摘要

Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is a typical approach for improving yield and reliability. Cell-based design methodologies are widely adopted in the industry for application-specific integrated circuits. Standard cells are effective for increasing the insertion rate of redundant via1s in cell-based designs. This study proposes an efficient library check and staggered pin arrangement approach that compares redundant via1 insertion rate in different configurations such as double-via and rectangle-via. To compare the variability in standard cell (SC) libraries, accurate characterization results are provided. Moreover, the proposed SC library is easily implemented in all currently available routers. The experimental results reveal that the proposed library improves total inserted redundant vias, total inserted redundant via1s, and total run time by 20.2%, 51.9%, and 42.3%, respectively. In double-via pattern, the proposed approach improves average via1 insertion rate by 14.6%. In rectangle-via pattern, the proposed approach achieves a 100% via1 insertion rate.