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Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

机译:亚阈值绝热逻辑在超低功耗应用中的实现

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Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.
机译:文献首次对绝热逻辑电路在弱反转或亚阈值状态下的行为进行了深入分析,以极大地改善超低功耗电路设计。这种新颖的方法在低速运行中非常有效,在低速运行中,功耗和寿命是关键而不是性能。已经实现了4位进位超前加法器(CLA)的原理图和布局,以显示所提出逻辑的可操作性。温度和过程参数变化对基于阈值绝热逻辑的4位CLA的影响也已单独解决。布局后的仿真表明,与逻辑等效的静态CMOS实现相比,亚阈值绝热单元可以节省大量能量。通过使用CADENCE SPICE Spectra在22纳米CMOS技术中进行的广泛仿真,可以验证结果。

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