Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths

摘要

The design, analysis, and implementation of an accurate delay circuit used to synthesize critical paths in a microprocessor system are presented. The delay circuit includes a novel 64-step programmable calibration delay line that is highly uniform across a wide range of supply voltages and a reconfigurable delay path with tunable delay sensitivity to voltage variations. The calibration delay line generates delay step in picosecond range, which is less than 1% of the clock cycle time for the microprocessor. The reconfigurable path is capable of increasing voltage sensitivity of the delay circuit by 40% and emulating the steeper frequency versus voltage slope of the microprocessor in low-voltage domain. The proposed circuit is implemented inside the critical path monitor block placed on a test microprocessor core fabricated using 22-nm silicon-on-insulator CMOS process. Measurement results from nine test cores show that the circuit tracks microprocessor timing margin change with an error less than 1.3% of the core operating frequency over a wide supply voltage range.