A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

摘要

A static timing verifier is an important tool in the design of acomplex high performance VLSI chip such as an Alpha CPU. A timingverifier uses a simple and pessimistic delay model to identify criticalfailing paths in the design, which then need to be fixed. However, thepessimistic delay model results in a large number of correct paths beingidentified as failing paths, possibly leading to wasted designresources. Therefore, each critical path identified by the timingverifier needs to be analyzed using a circuit simulator such as SPICE inorder to confirm that it is a real failure. Setting up such a simulationis complex, especially when the critical path consists of structuresappearing in a datapath of the CPU. In this paper, we present algorithmsfor the construction of a model for simulating the maximum delay througha critical path. This technique has been used to analyze severalcritical paths during the design of a 300 MHz Alpha CPU