Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms

摘要

Back-end wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework that contains modules for back-end time-dependent dielectric breakdown, electromigration, and stress-induced voiding is proposed to analyze circuit layout geometries and interconnects to estimate state-of-the-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress temperature, linewidth, and cross-sectional areas of each interconnect/via within the microprocessor system. Different workloads are considered to evaluate aging effects in single-core microprocessors running applications with realistic use conditions.