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Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

机译:基于多数的并行测试多个相同内核的测试访问机制

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The increased use of multicore chips diminishes per-core complexity and also demands parallel design and test technologies. An especially important evolution of the multicore chip has been the use of multiple identical cores, providing a homogenous system with various merits. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores and identifying faulty cores to derate the chip by excluding it. Instead of typical test response data from the cores, the test output data used in this paper are the majority values, that is, the typical test responses from the cores. All the cores can thereby be tested in parallel and test costs (in both test pins and test time) are exactly the same as for a single core. The proposed TAM can be implemented with on-chip comparators and majority analyzers. The experimental results in this paper show that the proposed TAM can test multiple cores with minimal test pins and test time and with hardware overhead of %.
机译:多核芯片使用的增加减少了每核的复杂性,还需要并行设计和测试技术。多核芯片的一个特别重要的发展就是使用了多个相同的核,从而提供了具有各种优点的同质系统。本文介绍了一种新颖的测试访问机制(TAM),用于并行测试多个相同的内核,并确定有故障的内核,以通过排除芯片来降低芯片的性能。本文使用的测试输出数据不是大多数核心的典型测试响应数据,而是多数值,即核心的典型测试响应。从而可以并行测试所有内核,并且测试成本(在测试引脚和测试时间上)与单个内核完全相同。可以使用片上比较器和多数分析器来实现建议的TAM。本文的实验结果表明,提出的TAM可以用最少的测试引脚和测试时间以及%的硬件开销来测试多个内核。

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