Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

摘要

Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds of clock cycles to achieve synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in a cell-based design flow. The proposed ADDLL circuit can acquire the phase of a clock signal from 60-MHz frequency to 1.2-GHz frequency. In this paper, the digitally controlled delay line (DCDL) is resettable such that our constant acquisition-cycle DLL algorithm can apply. This paper realizes the DCDL using lattice delay units in a linear manner, so the delay profile of our DCDL shows good linearity. On the other hand, the proposed ADDLL algorithm can effectively eliminate the harmonic lock. The ADDLL chip is implemented using the Artisan-TSMC-0.18-μm CMOS cell library. The measured power consumption of the chip is 16.2 mW at 1.2-GHz clock frequency and at 1.8 V supply voltage. The rms jitter is 1.63 ps and the peak-to-peak jitter is 12.8 ps. Both are measured at 1.2-GHz clock frequency.