Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling

摘要

Extensive research has been conducted on a statistical timing analysis of digital integrated circuits in the existence of statistical parameter variations. However, the proposed methods either lack accuracy or efficiency, which avoids coming up with an industry standard tool. Despite this fact, there is a certain consensus that Monte Carlo (MC) methods are accurate, so that they are called golden. In this paper, we propose novel techniques to combine control variates with importance sampling in order to come up with a new timing yield estimator as accurate as SPICE-based standard MC (STD-MC) but much faster. The performance of three different estimators, two of which are proposed in this paper, is compared through experiments, and the results show that the precise SPICE simulation-based STD-MC method can be accelerated about 260× on the average without sacrificing any accuracy.