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首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes
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Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes

机译:卷积码的MIMO无线通信中可配置联合检测与解码算法与架构

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摘要

This paper presents an algorithm and a VLSI architecture of a configurable joint detection and decoding (CJDD) scheme for multi-input multioutput (MIMO) wireless communication systems with convolutional codes. A novel tree-enumeration strategy is proposed such that the MIMO detection and decoding of convolutional codes can be conducted in single stage using a tree-searching engine. Moreover, this design can be configured to support different combinations of quadrature amplitude modulation (QAM) schemes as well as encoder code rates, and thus can be more practically deployed to real-world MIMO wireless systems. A formal outline of the proposed algorithm will be given and simulation results for 16-QAM and 64-QAM with rate-1/2 and rate-1/3 codes will be presented showing that, compared with the conventional separate scheme, the CJDD algorithm can greatly improve bit error rate (BER) performance with different system settings. In addition, the VLSI architecture and implementation of the CJDD approach will be illustrated. The architectures and circuits are designed to support configurability and flexibility while maintaining high efficiency and low complexity. The postlayout experimental results for 16-QAM and 64-QAM with rate-1/2 and rate-1/3 codes show that, compared with the previous configurable design, this architecture can achieve reduced or comparable complexity with improved BER performance.
机译:本文提出了一种用于卷积码的多输入多输出(MIMO)无线通信系统的可配置联合检测和解码(CJDD)方案的算法和VLSI架构。提出了一种新颖的树枚举策略,使得可以使用树搜索引擎在单级中进行卷积码的MIMO检测和解码。而且,该设计可以配置为支持正交幅度调制(QAM)方案以及编码器编码率的不同组合,因此可以更实际地部署到实际的MIMO无线系统中。给出了该算法的正式轮廓,并给出了带有码率1/2和码率1/3的16-QAM和64-QAM的仿真结果,表明与传统的单独方案相比,CJDD算法可以通过不同的系统设置大大提高误码率(BER)性能。此外,还将说明VLSI架构和CJDD方法的实现。这些架构和电路旨在支持可配置性和灵活性,同时保持高效率和低复杂度。具有速率1/2和速率1/3码的16-QAM和64-QAM的后期布局实验结果表明,与以前的可配置设计相比,该体系结构可以实现降低的或相当的复杂性,并提高BER性能。

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