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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration
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PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration

机译:PR-TCAM:使用部分重配置的Xilinx FPGA上的高效TCAM仿真

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Modern field-programmable gate arrays (FPGAs) provide a vast amount of logic resources that can be used to implement complex systems while providing the flexibility to modify the design once deployed. This makes them attractive for software-defined networks (SDNs) applications, and, in fact, most vendors provide the building blocks needed for those applications, which include basic packet classification functions such as exact match, longest prefix match, and match with wildcards. Those are needed for different functions such as routing, security filtering, monitoring or quality of service. The match with wildcards can be done using ternary content addressable memories (TCAMs). TCAMs can be implemented as independent standalone devices or as Internet Protocol (IP) blocks that are used inside networking application-specific integrated circuits (ASICs) such as switching ICs. In both cases, the cells of a TCAM are more complex than that of a normal memory and also than that of a binary content addressable memory (CAMs). This is due to the more complex matching that they need to implement. As FPGAs are used in many different applications, it does not make sense to include TCAM blocks inside them as they would be used only in a small fraction of the systems. Therefore, TCAMs are emulated using the logic resources available inside the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed, some of them based on the use of the logic resources and others on the use of the embedded memory blocks available on the FPGA. In this brief, a technique to efficiently emulate TCAMs on Xilinx FPGAs is presented. The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules. The proposed scheme has been compared to existing implementations and the results show that it can achieve significant savings in resource usage. In addition, it enables the use of all the LUTs in the device for TCAM implementation, something that is not supported by existing approaches that use LUTRAMs.
机译:现代的现场可编程门阵列(FPGA)提供了大量的逻辑资源,这些资源可用于实现复杂的系统,同时在部署后可以灵活地修改设计。这使它们对于软件定义网络(SDN)应用程序具有吸引力,并且实际上,大多数供应商都提供了这些应用程序所需的构件,其中包括基本的数据包分类功能,例如精确匹配,最长前缀匹配以及与通配符匹配。路由,安全过滤,监视或服务质量等不同功能需要这些功能。可以使用三态内容可寻址存储器(TCAM)与通配符进行匹配。 TCAM可以实现为独立的独立设备,也可以实现为在网络专用集成电路(ASIC)(例如交换IC)内部使用的Internet协议(IP)块。在这两种情况下,TCAM的单元都比普通存储器的单元复杂,也比二进制内容可寻址存储器(CAM)的单元复杂。这是由于他们需要实施更复杂的匹配。由于FPGA在许多不同的应用中使用,因此在其中包含TCAM块是没有意义的,因为它们只会在很小一部分系统中使用。因此,使用FPGA内部可用的逻辑资源来仿真TCAM。近年来,已经提出了许多在FPGA上仿真TCAM的方案,其中一些基于逻辑资源的使用,其他基于FPGA上可用的嵌入式存储模块的使用。在本文中,提出了一种在Xilinx FPGA上有效仿真TCAM的技术。所提出的方案基于查找表(LUT)的使用和部分重新配置,以在支持添加和删除规则的同时更有效地利用FPGA资源。将该方案与现有实施方案进行了比较,结果表明该方案可以节省大量资源。此外,它允许将设备中的所有LUT都用于TCAM实施,而使用LUTRAM的现有方法不支持这种情况。

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