首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC–DC Converter With Intrinsic Parasitic Charge Recycling
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A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC–DC Converter With Intrinsic Parasitic Charge Recycling

机译:具有固有寄生电荷回收功能的单片电压可伸缩斐波纳契开关电容器DC-DC转换器

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Switched-capacitor converter (SCC) features a compact solution due to its magnetic-less structure, which fulfills the high density requirement in low power applications. Compared to other SCC topologies, Fibonacci switched-capacitor converter (FSC) utilizes the least number of flying capacitors to perform any voltage conversion. This paper proposes a monolithic voltage-scalable FSC, which can be used in energy harvesting applications. The challenges to implement on-chip FSC are addressed. The parasitic charge loss is substantial in FSC. Therefore, a charge recycling technique exploiting the presence of parasitic capacitors in each other phase of FSC has been employed resulting in 27% reduction in the power loss, which improves the overall efficiency by 12.7%. For a proof of concept, the proposed converter is implemented in 0.5-mu m CMOS technology on 4-mm(2) die area. The postlayout simulation is carried out using Virtuoso ADE. With 0.3-V input voltage, the system achieves 47.5% peak power efficiency with 5-mu W load.
机译:开关电容器转换器(SCC)的无磁结构具有紧凑的解决方案,可满足低功率应用中对高密度的要求。与其他SCC拓扑相比,斐波那契开关电容器转换器(FSC)使用最少数量的飞跨电容器来执行任何电压转换。本文提出了一种单片可缩放电压的FSC,可用于能量收集应用。解决了实施片上FSC的挑战。在FSC中,寄生电荷损失很大。因此,已经采用了在FSC的每一相中利用寄生电容器的电荷回收技术,从而使功率损耗降低了27%,从而使总体效率提高了12.7%。为了进行概念验证,建议的转换器在0.5mm CMOS技术中的4mm(2)芯片面积上实现。使用Virtuoso ADE进行后布局仿真。输入电压为0.3V时,系统在5μW负载下达到47.5%的峰值功率效率。

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