Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

摘要

This paper introduces a technique, called scalable parasitic charge redistribution (SPCR), that reduces the parasitic bottom-plate losses in fully integrated switched-capacitor (SC) voltage regulators up to any desired level. This is realized by continuously redistributing the parasitic charge in-between phase-shifted converter cores. Because earlier models described the ratio of this parasitic coupling to the flying capacitance as the only limiting factor on the achievable fully integrated efficiency, the use of SPCR allows SC converters to achieve efficiencies previously deemed impossible. Transistor leakage is shown to be another limiting factor and is added to existing models which are then used to prove the effectiveness of SPCR over a wide range of power densities (up to 10 W/mm2) and technological parameters. The implementation of SPCR requires little overhead thanks to the use of charge redistribution buses. A 1/2 converter is fabricated in a 40 nm bulk CMOS technology that demonstrates SPCR by achieving a record efficiency for fully integrated closed-loop SC converters of 94.6%.