An improved switched-capacitor based charge redistribution successive approximation analog to digital converter (ADC)

摘要

This invention relates to an improved binary-weighted, switched-capacitor, charge-redistribution successive approximation Analog-to-Digital Converter (ADC) characterized in that it includes an adjusting mechanism for adding a charge corresponding to one-half of the Least Significant Bit (LSB) of said ADC to the charge stored in the switched capacitor array after the sampling phase of said ADC so as to provide a quantization error that is evenly distributed between +0.5 LSB and -0.5 LSB, without the need for any additional processing clock cycles.