Integrating Semiconductor Manufacturing Efficiency

摘要

Experience has shown that the cost of design, device compatibility and the impending applications has been driving the complexity of the SMT process compatible semiconductor packages. The other drivers have been device reliability, yield and efficiency during realtime applications. The increased complexity of the present package design, device and performance are driving a need to integrate the design and manufacturing process of SMT compatible devices. There is an increased requirement to trade optical, electronic, mechanical, magnetic and thermal data between the silicon chip and the package design to estimate performance and reliability. Advanced packaging trends, especially below the 90 nm range, are driving pin count, lead pitch, power use, sensitive electrical and stress transients toward a higher real-time simulation of the integrated package and design. The telecom, computer and consumer segments are converging to impose new challenges that the SMT assembly industry must face in the near future.