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Design of high breakdown voltage GaN vertical HFETs with p-GaN buried buffer layers for power switching applications

机译:具有p-GaN埋入缓冲层的高击穿电压GaN垂直HFET的设计,用于电源开关应用

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摘要

To achieve a high breakdown voltage, a GaN vertical heterostruc-ture field effect transistor with p-GaN buried layers (PBL-VHFET) is proposed in this paper. The breakdown voltage of this GaN-based PBL-VHFFT could be improved significantly by the optimizing thickness of p-GaN buried layers and doping concentration in PBL. When the GaN buffer layer thickness is 15 u.m, the thickness, length and p-doping concentration of PBL are 0.3 u.m, 2.7 urn, and 3 × 10~(17)cm~(-3), respectively. Simulation results show that the breakdown voltage and on-resistance of the device with two p-GaN buried layers are 3022 V and 3.13 mΩ cm~2, respectively. The average breakdown electric field would reach as high as 201.5 V/μm. Compared with the typical GaN vertical heterostruc-ture FETs without PBL, both of breakdown voltage and average breakdown electric field of device are increased more than 50%.
机译:为了实现高击穿电压,本文提出了具有p-GaN埋层的GaN垂直异质结场效应晶体管(PBL-VHFET)。通过优化p-GaN埋层的厚度和PBL中的掺杂浓度,可以显着改善这种基于GaN的PBL-VHFFT的击穿电压。当GaN缓冲层厚度为15μm时,PBL的厚度,长度和p掺杂浓度分别为0.3μm,2.7μm和3×10〜(17)cm〜(-3)。仿真结果表明,具有两个p-GaN埋层的器件的击穿电压和导通电阻分别为3022 V和3.13mΩcm〜2。平均击穿电场将高达201.5 V /μm。与不带PBL的典型GaN垂直异质结FET相比,器件的击穿电压和平均击穿电场均增加了50%以上。

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  • 来源
    《Superlattices and microstructures》 |2015年第7期|251-260|共10页
  • 作者单位

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China,Department of Electronic and Electrical Engineering, The University of Sheffield, Mappin Street, Sheffield S1 3JD, UK;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China;

    Science and Technology of ASIC Lab, Hebei Semiconductor Research Institute, Shijiazhuang 050051, PR China;

    Science and Technology of ASIC Lab, Hebei Semiconductor Research Institute, Shijiazhuang 050051, PR China;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, PR China;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    GaN HFET; Vertical; Heterostructure; Breakdown; Buried buffer layer;

    机译:GaN HFET;垂直;异质结构分解;埋入缓冲层;

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