Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

摘要

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length L_(ED) of 10 nm and source-side spacer length L_(ES) of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain A_v, unity-gain cut-off frequency f_T and maximum frequency of oscillations f_(MAX) by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO_2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak A_v while decreasing both peak f_T and f_(MAX). The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at L_(ED) = 10 nm with a SiO_2 spacer.