Analog/RF Performance Investigation of Nanoscale Gate-Underlap Single and Double Gate Silicon-On-Insulator MOSFETs with High-k Stack on Spacer

摘要

This work is facilitating for the improvement of performance of double gate (DG) and single gate (SG) Silicon-on-Insulator (SOI) MOSFETs using high-k (nitride) dielectric stack on source/drain (S/D) extension region (spacer). The results from 2D-ATLAS device simulator show that high-k dielectric spacer reduces the short-channel effects such as Drain Induced Barrier Lowering (DIBL), Subthreshold slope (S.S) due to eminent vertical fringing electric field. The high-k dielectric spacer ameliorate the I-on/I-off, transconductance, g(m) and voltage gain, A(v) of the DG and SG-SOI MOSFETs compared to the same devices with conventional spacer. Further more analog/RF performance simulation results reveal an improvement of A(v) by approximate to 52% and approximate to 60%, an increase of approximate to 20% and approximate to 40% in the case of cut-off frequency f(MAX) an increase of approximate to 19.23% and approximate to 25% in the case of maximum frequency of oscillation f(MAX) values of DG and SG-MOSFETs, respectively, with high-k spacer compared to conventional spacer. The results suggest that DG-SOI MOSFETs with high-k spacer can be available option (because of superior f(T) and f(MAX), which are due to higher gm and lower output conductance, g(ds)) for using high-frequency analog circuits applications such as Low Noise Amplifier (LNA) and Mixer.