A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2)latch and its application in a dual-modulus prescaler

摘要

A high speed dual-phase dynamic-pseudo NMOS ((DP)2)nlatch using clocked pseudo-NMOS inverters is presented. Compared to thenconventional D-latch, this circuit has a higher maximum operatingnfrequency and consumes lower dynamic power at a given operatingnfrequency. The latch has been demonstrated by utilizing it in thensynchronous counter section of a dual-phase dual-modulus prescalernimplemented in a 0.8 Μm CMOS process. The maximum operating frequencynfor the prescaler at 3 V supply voltage is 1.3 GHz, while the powernconsumption is 9.7 mW. This power consumption is significantly lowernthan those of the previously reported prescalers implemented in 0.8nΜm CMOS processes. The 9.7 mW power consumption at 1.3 GHz alsoncompares favorably to the 24 mW power consumption of the 1.75 GHznprescaler using MOS current mode latches implemented in a 0.7 Μm CMOSnprocess. A 25% reduction of the maximum operating frequency for a ~60%nreduction of the power consumption should be a useful tradeoff