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3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

机译:使用硅通孔的3D硅集成和硅封装技术

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System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 μm) interconnection is described. This silicon carrier package contains silicon through-vias and offers > 16 × increase over standard chip I/O, a 20 × to 100 × increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."
机译:片上系统(SOC)和封装系统(SOP)技术各有优势,具体取决于应用程序需求。随着系统设计师和设计人员利用不断增长的CMOS技术密度,出现了一系列二维和三维硅集成技术,这些技术可能会支持下一代大批量电子应用程序,并可能服务于高性能计算应用程序。本文将讨论一些新兴技术,这些技术为提高电路性能或降低功耗提供了机会。硅上硅集成可以包括片上三维(3-D)集成,或者可以利用芯片堆叠或封装上的芯片集成。共同的技术特征包括硅通孔,高I / O互连以及作为3D集成电路的硅上硅,集成芯片堆栈或具有无源功能或高带宽布线的硅上硅封装。与增加的片上去耦或安装在封装外围或封装下方的芯片外分立电容器相比,具有集成功能(如去耦电容器)的硅中介层上的硅芯片可以提供更好的模块架构。描述了具有精细间距(50μm)互连的先进硅载体封装技术。这种硅载体封装包含硅通孔,与标准芯片I / O相比增加了16倍以上,与传统的有机和陶瓷封装相比,布线密度提高了20倍至100倍,并允许集成高性能无源器件。硅载体技术支持光刻缩放,并为已知的良好管芯(KGD)晶圆测试提供了基础。可以考虑将其用于许多应用中,包括光电(OE)收发器,具有集成去耦电容器的硅中介层以及将异类裸片集成在一起形成单个“虚拟芯片”的微型多芯片模块(MMCM)。

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