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MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

机译:用于非易失性交叉开关存储阵列的基于MIEC(混合离子电子导电)的访问设备

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Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (> 1000×1000 device) arrays at low power tends to require quite large (> 1e7) ON-to-OFF ratios (between the Currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate Ads have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line-which would eliminate any opportunity for 3D stacking-has been difficult. We review our work at IBM Research-Almaden on high-performance Ads based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based Ads offer large ON/OFF ratios (>le7), a significant voltage margin V_m (over which current <10 nA), and ultra-low leakage (< 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions < 30 nm and thicknesses < 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based Ads shows that their operation depends on Cu~+ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (< 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V.
机译:几种吸引人的应用程序要求将忆阻器件(或其他电阻性非易失性存储器(NVM))组织为大型,密集包装的交叉开关阵列。虽然电阻型NVM器件通常具有一定程度的固有非线性(通常为3-30倍对比度),但是大型(> 1000×1000器件)阵列在低功率下的操作往往需要相当大(> 1e7)的开-关比率(在高电压和低电压下通过的电流之间)。达到如此大的非线性的一条途径是将独特的访问设备(AD)与每个带有状态的电阻性NVM元件一起使用。尽管此类AD不需要存储数据,但其要求清单几乎与存储设备的规格要求一样具有挑战性。已经提出了几种候选广告,但是很难获得高性能而不需要单晶硅和/或生产线前端的高处理温度,这将消除3D堆叠的任何机会。我们在IBM Research-Almaden上审查了有关基于含铜的混合离子电子传导(MIEC)材料的高性能广告的工作。这些设备只需要生产线后端的低处理温度,使其非常适合于实现多层交叉开关阵列。基于MIEC的广告具有较大的开/关比(> le7),显着的电压裕量V_m(在该范围内电流<10 nA)和超低泄漏(<10 pA),同时还提供了相所需的高电流密度-更改存储器以及高性能RRAM所需的全双极性操作。可扩展至关键横向尺寸<30 nm和厚度<15 nm,在大型(512 kBit)阵列中分布紧密且良率达100%,超低泄漏状态的长期稳定性以及接通时间小于50 ns所有被证明。这些基于MIEC的Ads的数值模型表明,它们的操作取决于Cu〜+介导的空穴传导。电路仿真显示,虽然缩放后的MIEC器件适用于开关电压较低(<1.2 V)的电阻型NVM器件的大型交叉开关阵列,但堆叠两个MIEC器件可以支持开关电压高达2.5 V的大型交叉开关阵列。

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