Impact of process-induced variability on the performance and scaling of Ge_2Sb_2Te_5 Phase-change memory device

摘要

The process-induced variability in nanoscale phase-change memory (PCM) devices is of utmost importance for the development of reliable single-bit/multi-bit data storage devices. In this study, the influence of structural and interfacial parameters on the performance of Ge2Sb2Te5 (GST) PCM device is systematically investigated using Plackett-Burman design of experiment method. Five important structural parameters, (i) heater (TiN) radius (HR), (ii) heater height, (iii) GST radius (W-GST ), (iv) GST thickness, and (v) top electrode thickness, and along with three interfacial parameters namely, (i) thermal boundary resistance (TBR) between GST and TiN interface (ii) TBR between GST and SiO2 interface, and (iii) electrical interface resistance (EIR) between GST and TiN interface are considered for the study. Furthermore, to understand the impact of scaling, the performance metrics i.e. RESET resistance (R-RESET), SET resistance (R-SET), RESET power (P-RESET) and SET power (P-SET) of an isotropically scaled-down device with a HR of 10 nm are extracted and compared against the reference device of 50 nm HR. The TCAD simulation results reveal that HR and W-GST are the most dominant structural parameters for the output metrics and the analysis shows that W-GST/HR ratio should be maintained between 2.7 (30 nm/11 nm) and 4.5 (45 nm/10 nm) to offer reliable RESET operation. Among the interfacial parameters, GST/TiN EIR is the most significant controlling parameter for P-RESET/P-SET metrics, whereas GST/TiN TBR plays an important role in achieving better R-RESET/R-SET. Hence, our findings of the most and least sensitive input parameters can be effectively used for the better optimization of RESET/SET pulse parameters to achieve reliable programming of PCM devices in the future technology nodes.