The last few editions of the International Technology Roadmap for Semiconductors (ITRS) have called for the development and improvement of chip-package-board codesign capabilities. Faster, more complex chips with ever-increasing numbers of I/Os and power connections drive this need, as well as the increasing number of sys-tems-in-package (SiPs). Some surprising cost factors are also driving codesign. Earlier this year, Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu), an IC foundry, released version 5.0 of its reference design flow. It includes capabilities for integrating the design of the chip and package, using tools from various companies, including Cadence (San Jose) and Optimal Corp. (San Jose). Timing and substrate routing challenges were among the reasons given for doing this, but the primary reasons were I/O and power planning.
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