This dissertation is concerned with issues arising in constructing systems using area-array flip-chip solder bumps to attach integrated circuit chips to a thin film multichip module (MCM) substrate. The concepts to be demonstrated were using the existing MCM power and ground planes to distribute power/ground to the IC as opposed to having global power/ground networks on the chips and using the MCM signal planes to distribute a low-skew clock, which would enter each chip through multiple insertion points (i.e., solder bumps). A test system which implemented the Data Encryption Standard (DES) was designed and built utilizing these concepts. This system ran at a throughput of over 7Gb/s, which made it the highest-reported DES hardware throughput at the time. Clock skew was measured to be 15ps.; The other major topic of the dissertation is an investigation of high-density I/0 systems using capacitively-coupled I/0, in which driver and receiver are coupled through parallel metal plates instead of a wire. Using linear models, an expression for signal/noise ratio in such a system is derived and compared to circuit simulation results. A methodology for constructing such systems is introduced, and the tradeoffs involved in designing such systems are discussed.
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