A FPGA implementation of the Unidirectional Systolic Array for the Matrix-Vector Multiplication

摘要

The systolic processing offers the possibility of solving a large number of standard problems on multicellular computing devices with autonomous cells (Processing Elements - PEs). The Matrix-Vector Multiplication problem is one of the most representative candidates for a systolic based solution. Herein, an implementation of the Unidirectional Linear Systolic Array (ULSA) for the Matrix-Vector multiplication problem proposed in (Milovanovic, et al., 2006) is presented, based on the FPGA technology, and some performance evaluation issues are discussed.