VHDL Implementation of PPR Systolic Array Architecture for Polynomial GF(2m) Multiplication.

摘要

This thesis is devoted to efficient VHDL design of Systolic Array Architecture for Polynomial GF(2m) multiplication. The hardware implements the Processor Elements (PE) and Systolic Array design for Progressive Product Reduction (PPR) method proposed by Gebali and Atef [2]. The experiment first implements a simpler irreducible polynomials GF(2 5) based on the defined algorithms for PPR in order to confirm the functionality of the design and then tries the bigger value of m for GF(2133) and GF(2233), recommended by NIST. The thesis is comparing the three designs based on their power consumption, Maximum Data path delay and device utilization. It also looking in to the different optimization method for the designs and recommends a design optimization based on circuit modification.