Enhanced architecture for programmable logic controllers targeting performance improvements

摘要

Programmable logic controllers (PLCs) are massively used as the central processing control units in industrial automation solutions. Unfortunately, the lack of performance of these controllers requires coupling specific drivers to the PLCs to enable deterministic response in time-sensitive real-time applications, thus reducing the importance of the PLCs in the entire automation systems. Current solutions do not focus on PLC performance, and it is, therefore, safer to use the design pattern with these specific drivers when required. This situation does not give PLC users of those solutions full control of the provided automation and, consequently, it increases the price of the entire system, as well as the need for spare parts. To put PLCs back as central processing units of industrial automation technology and to reduce the need for specific drivers, this work proposes a novel architecture with enhanced improvements based mainly on the concepts of data flow computation and memoization technique to boost PLC performance. Evaluations made on the proposed design demonstrate a reduction of 95% in the proposed architecture's scan time and show significant performance boost even in small-scale, didactic and straightforward examples. Moreover, the experimental evaluations also have demonstrated the potential for continued performance improvement with the increase of the program size.