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Programmable logic controller performance enhancement by field programmable gate array based design

机译:通过基于现场可编程门阵列的设计提高了可编程逻辑控制器的性能

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摘要

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. (C) 2014 ISA. Published by Elsevier Ltd. All rights reserved.
机译:由于是串行执行,PLC是现代自动化系统的核心元素,因此存在速度慢和扫描时间短的局限性。已经提出了基于FPGA的基于并行执行机制的改进PLC设计,以增强性能和灵活性。 Modelsim作为仿真平台,VHDL用于在FPGA中转换,集成和实现逻辑电路。赛灵思用于实施测试和VB的Spartan套件已用于GUI开发。该设计的显着优点包括成本效益,小型化,用户友好性,简单性,以及更低的功耗,更短的扫描时间和更高的速度。已开发并成功测试了各种功能和应用程序,例如典型的PLC和工业警报信号器。已经报告了仿真,设计和实现的结果。 (C)2014 ISA。由Elsevier Ltd.出版。保留所有权利。

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