A study on the performance impact of programmable logic controllers based on enhanced architecture and organization

摘要

Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these devices, the typical role of PLCs in automation systems becomes restricted to a simple controller, since applications with more sophisticated computational requirements tend to be handled by external processing units along with the PLCs. To solve this issue, this work improves novel architecture proposals based on data flow machines, circuit simulation theory, and the memoization technique to achieve a performance boost based on the scan time reduction. Along with the architectural improvements, this paper evaluates the impact of different execution units' types and quantities in a cycle-accurate simulator (CAS) that was specially developed to simulate the PLC cores. Furthermore, in order to perform a robust and complete evaluation, the silicon areas of the simulated architectures are calculated using the McPAT framework to establish the performance/area relationship of the simulated cores. Evaluation results show best scan time reductions of up to 68% for cores with single execution units and up to 89% for cores with multiple execution units, as well as a best-case of 50% scan time reduction with an acceptable impact on the silicon area. Lastly, the evaluation of the results of the proposed improved cores with multiple execution units shows that they outperform the theoretical performance limit of multiple execution units based on Amdahl's law up to 4 execution units. (C) 2020 Elsevier B.V. All rights reserved.