Area-time efficient multi-modulus adders and their applications

摘要

Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are proposed for multi-modulus adders that support the most common moduli cases in RNS channels, that is, modulo 2~n - 1, 2~n and 2~n + 1. The proposed architectures use parallel prefix carry computation units composed of log2n levels. The experimental results show that the resulting adders are significantly faster and/or smaller than the earlier proposals. Multi-modulus sub-tractors, multipliers and squarers that rely on the use of the proposed multi-modulus adders are also presented. The last two are shown experimentally to outperform the currently most efficient ones in area, delay and dynamic power dissipation terms.