Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

摘要

Through-silicon vias (TSVs), being one of the key enabling technologies for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and even less experimental failure analysis has been reported in the literatures. In this paper, TSV samples have been fabricated and tested under thermal-shock test from -55℃ to 125℃. Various experimental techniques have been used to carry out the failure mechanism analysis. Both Cu/SiO_2 interfacial separations and SiO_2/Si cohesive cracking were identified at various locations along the Cu/SiO_2/Si interfaces. Finite-element based fracture analysis models have also been developed to understand the interfacial/cohesive crack initiation and propagation. A centered finite difference approach (CFDA) based on Griffith's energy balance has been developed for the axisymmetric crack propagation analysis. Also, the virtual crack closure technique (VCCT) has been applied for the axisymmetric interfacial/cohesive crack analysis. Both methods match perfectly with each other for linear elastic analysis, and agree well for elastic-plastic analysis. The fracture analysis results match the experimental observations, and also provide insight on the reason behind different failure mechanisms.