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Realistic non-destructive testing of integrated circuit bond wiring using 3-D X-ray tomography, reverse engineering, and finite element analysis

机译:使用3-D X射线断层扫描,逆向工程和有限元分析对集成电路键合布线进行实际无损测试

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摘要

Within industries that manufacture and/or utilize semiconductor devices, integrated circuit (IC) bond wiring is tested for product assurance and counterfeit detection purposes through invasive and destructive probing. The examined unit is either partially damaged or fully destroyed during these tests and the uncertainties that existed prior to testing reappear when a new unit must replace the probed unit. Because packaged circuits serve such diverse roles in countless critical systems across many applications, there is a strong need for robust, quick, and non-destructive testing. As of now, methods to non-destructively test these components involve either simplified geometric modeling and finite element analyses, which make concessions to accuracy, or include more accurate forms of geometric acquisition but remain untested, unverified, and computationally expensive. The goals of this study are to test the validity of micro-CT as a tool to import accurate bond wire geometries to single- and multi physical finite element testing and to produce a practical methodology for the image acquisition, processing, and simulation of integrated circuit bond wires with a focus on practicality and industrial applicability. A reverse engineering technique is examined as a valid simplification to the geometries retrieved from micro-CT. The reverse engineered geometry from micro-CT is then tested within a finite element simulation with the loading data gathered from a traditional destructive bond wire pull-test to examine its similarity. The results show that the proposed methodology can closely mirror the destructive test by highlighting the correct location of probable failure with the corresponding stress values in excess of the material's strength limits. In addition, the methodology reduces the finite element computational expense by a factor of four and produces a CAD editable model for geometric alteration or other finite element testing environments; similar to the files created by part manufacturers prior to production. The differences being that the model can include production process-related variations and can be utilized by an end-user seeking validation for a given application. The broader implications of this methodology include its application to iterative product design and extension to multi-physical, dynamic, and/or inordinately expensive testing conditions.
机译:在制造和/或利用半导体器件的行业中,通过侵入性和破坏性探测对集成电路(IC)键合布线进行了产品保证和伪造检测目的测试。在这些测试过程中,被检查的单元被部分损坏或完全破坏,并且当必须更换被测单元时,会再次出现测试前存在的不确定性。由于封装电路在许多应用中的无数关键系统中扮演着如此多样化的角色,因此迫切需要鲁棒,快速且无损的测试。到目前为止,用于非破坏性测试这些组件的方法涉及简化的几何建模和有限元分析,这些都对精度有所让步,或者包括更精确的几何采集形式,但仍未经测试,未经验证且计算量大。这项研究的目的是测试微型CT作为将准确的键合线几何图形导入单物理和多物理有限元测试的工具的有效性,并为集成电路的图像采集,处理和仿真提供一种实用的方法。键合线,注重实用性和工业实用性。反向工程技术被视为对从微型CT检索到的几何图形的有效简化。然后,在有限元模拟中对来自微型CT的反向工程几何进行测试,并使用从传统破坏性键合线拉力测试中收集的载荷数据来检查其相似性。结果表明,所提出的方法可以通过突出可能失效的正确位置以及相应的应力值超过材料强度极限的正确位置来密切反映破坏性测试。此外,该方法将有限元的计算费用减少了四倍,并为几何变更或其他有限元测试环境生成了可编辑的CAD模型;与零件制造商在生产之前创建的文件类似。不同之处在于该模型可以包括与生产过程相关的变体,并且可以由寻求对给定应用程序进行验证的最终用户使用。这种方法的广泛含义包括其在迭代产品设计中的应用以及对多物理,动态和/或非常昂贵的测试条件的扩展。

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