Systematic design of the pipelined analog-to-digital converter with radix < 2

摘要

A systematic design of the pipelined analog-to-digital converter with radix < 2 is described. A 50 MHz, 3.3 V, 10-bit pipelined analog-to-digital converter has been implemented in a 0.25-μm CMOS technology using radix < 2 architecture. It achieves more than 54 dB signal-to-noise plus distortion ratio in Nyquist signal sampling at 3.0 V (10% lower than the 3.3 V nominal value) over -40 to +120℃ temperature range with a full-scale sinusoidal input. The IM3 of the converter, which is an important parameter for the OFDM based systems, is less than -64 dB. Non-linearity is reduced through digital self-calibration and correction. The digital calibration procedure takes less than 24 μS and can be done either on power up or intermittently. The layout area is 1.8 mm X 1.2 mm. The converter consumes 100mA out of a 3.3 V supply including the reference circuitry, analog cells, and all digital blocks at full-scale Nyquist sampling speed.