Effect of SiO_2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

摘要

In this study, we investigated the effect of various SiO_2 tunnel layers on the characteristics of charge trap memories with Metal/SiO_2/Si_3N4/SiO_2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO_2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO_2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO_2 and LP-TEOS SiO_2 showed larger breakdown voltages with more uniform thickness than thermal SiO_2 on poly-Si channels. MONOS devices with radical SiO_2 and LP-TEOS SiO_2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO_2. In particular, the MONOS device with LP-TEOS SiO_2showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO_2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO_2 tunnel dielectrics.