Voltage dependences of parameter drifts in hot carrier degradation for n-channel LDMOS transistors

摘要

The reliability characterization in shallow trench isolation (STI) based n-channel lateral diffused metal-oxide-semiconductor (LDMOS) transistor has recently drawn much attention. A thorough investigation of the hot carrier degradation under various gate and drain stress biases are carried out to gain an insight on the bias dependences of the parameter drifts. The findings are supported by both experimental and the technology computer-aided design (TCAD) simulations data. Based on the results, the drain voltage (V_(DS)) parameter was found as a significant accelerating factor for the test. The analysis of HCI damage phenomenon on this device shows that the degradation mechanism is highly dependent on the stress voltage at the gate (V_(GS)).