TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors

摘要

A combined experimental and simulation analysis of the degradation mechanisms induced by hot carriers in a silicon-based split-gate n-channel LDMOS transistor featuring an STI structure is reported. In this regime, electrons can gain sufficient kinetic energy necessary to create charged traps at the silicon/oxide interface, thus inducing device degradation and causing the shift of the electrical parameters of the device. In particular, the onresistance degradation in linear regime has been experimentally characterized at different stress conditions and at room temperature. The hot-carrier degradation has been reproduced in the frame of TCAD simulations by using physical-based models aimed at reproducing the degradation kinetics. An investigation of the electron distribution function at different stress conditions and its dependence on the split-gate bias is carried out achieving a quantitative understanding of the role played by hot electrons in the hot-carrier degradation mechanisms of the device under test.