A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

摘要

Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-$mu$ m CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.